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1 m e m o r y all data sheets are subject to change without notice (858) 503-3300 fax: (858) 503-3301- www.maxwell.com 16-bit latchup protected adc 7805alp ?2005 maxwell technologies all rights reserved. 01.10.05 rev 9 f eatures : ? 16-bit organization latchup protection technology? r ad -p ak ? radiation-hardened against natural space radia- tion total dose hardness: - > 50 krads(si), depending upon space mission latchup converted to reset. - rate based on cross section and mission. package: - 28 pin r ad -p ak ? flat pack - 28 pin r ad -p ak ? dip 100 khz min sampling rate standard 10v input range advance cmos technology - 86 db min sinad with 20 khz input - single 5v supply operation - utilizes internal or external reference - full parallel data output - power dissipation: 132 mw max d escription : maxwell technologies? 7805alp high-speed analog-to-digital converter features a greater than 50 krad (si) total dose toler- ance, depending upon space mission. using mawell?s radia- tion-hardened r ad -p ak ? packaging technology, the 7805alp incorporates the commercial ads7805 from burr brown. this device is latchup protected by maxwell technologies? lpt? technology. the 7805alp, 16-bit sampling cmos a/d . the device contains a complete 16-bit capacitor-based sar a/d with s/h, reference, clock, interface for microprocessor use, and three-state output drivers. the 7805alp is specified at a 100 khz sampling rate, and guaranteed over the full tempera- ture range. laser-trimmed scaling resistors provide an indus- try-standard 10v input range, while the innovative design allows operation from a single 5v supply, with power dissipa- tion of under 132 mw. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. in a geo orbit, r ad -p ak ? provides greater than 50 krad (si) radiation dose tolerance. this product is available with screening up to maxwell technologies self-defiened class k. logic diagram
m e m o r y 2 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 t able 1. 7805alp p inout d escription p in n umber n ame d igital i/o d escription 1v in analog input. 2 agnd1 analog ground. used internally as ground reference point. 3 ref reference input/output. 2.2 f tantalum capacitor to ground 4 cap reference buffer capacitor. 2.2 f tantalum capacitor to ground. 5 agnd2 analog ground. 6 d15 (msb) 0 data bit 15. most significant bit (msb) of conversion results. when status is high*, d15 must not be driven high. 7 d14 0 data bit 14. when status is high*, d14 must not be driven high. 8 d13 0 data bit 13. when status is high*, d13 must not be driven high. 9 d12 0 data bit 12. when status is high*, d12 must not be driven high. 10 d11 0 data bit 11. when status is high*, d11 must not be driven high. 11 d10 0 data bit 10. when status is high*, d10 must not be driven high. 12 d9 0 data bit 9. when status is high*, d9 must not be driven high. 13 d8 0 data bit 8. when status is high*, d8 must not be driven high. 14 dgnd digital ground 15 d7 0 data bit 7. when status is high*, d7 must not be driven high. 16 d6 0 data bit 6. when status is high*, d6 must not be driven high. 17 d5 0 data bit 5. when status is high*, d5 must not be driven high. 18 d4 0 data bit 4. when status is high*, d4 must not be driven high. 19 d3 0 data bit 3. when status is high*, d3 must not be driven high. 20 d2 0 data bit 2. when status is high*, d2 must not be driven high. 21 d1 0 data bit 1. when status is high*, d1 must not be driven high. 22 d0 (lsb) 0 data bit 0. least significant bit (lsb) of conversion results. when status is high*, d0 must not be driven high. 23 status* 0 status when high indicates latchup protection is active and output data is invalid. capacitive loading should not exceed 1000 pf. 24 r/c iwith cs low and busy high, a falling edge of r/c initiates a new conversion. when status is high*, cs and r/c must not be driven high. 25 cs i internally or?d with r/c . if r/c low, a falling edge on cs initiates a new conver- sion. when status is high*, cs and r/c must not be driven high. 26 busy 0 at the start of a conversion, busy goes low and stays low until the conversion is completed and the digital outputs have been updated. 27 decplng supply voltage high speed decoupling pin. decouple to ground with 1.0 f ceramic capacitor. 28 v s supply input. nominally 5v. decouple to ground with 10 f tantalum capacitor.
m e m o r y 3 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 t able 2. 7805alp a bsolute m aximum r atings p arameter s ymbol m in t yp m ax u nit analog inputs v in cap ref -25 v s 9 -- -- -- 25 agnd2 - 0.3 -- v ground voltage difference dgnd agnd1 agnd2 -0.3 -0.3 -0.3 -- -- -- 0.3 0.3 0.3 v supply input v s -- 7 v digital inputs -0.3 -- vs + 0.3 v thermal impedance jc 11 c/w internal power dissipation -- -- 825 mw maximum junction temperature t j -- -- 165 c t able 3. 7805alp dc a ccuracy s pecifications (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter c onditions s ubgroups m in t yp m ax u nit integral linearity error -- -- 3 lsb differential linearity error -- -- 4, -1 lsb no missing codes 1 1. guaranteed by design 15 -- -- bits transition noise 2 2. typical rms noise at worst case transitions and temperatures. -- 1.3 -- lsb full scale error 3,4 3. measured with various fixed resistors. 4. full scale error is worst case - full scale or +full scale untrimmed deviation from ideal first and last code transitions, di vided by the transition voltage (not divided by the full-scale range) and included the effect of offset error. -- -- 0.5 % full scale error drift -- 7 -- ppm/ c bipolar zero error 3 -- -- 10 mv bipolar zero error drift -- 2 -- ppm/ c power supply sensitivity 4.8v < v s < 5.25v -- -- 8 lsb t able 4. 7805alp d igital i nputs (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit v il 1, 2, 3 -0.3 -- 0.8 v v ih 2.0 -- v s +0.3 v
m e m o r y 4 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 i il , i ih 1, 2, 3 -- -- 10 a t able 5. 7805alp a nalog i nputs (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit voltage ranges 1 1. tested by application of signal. 1, 2, 3 -10 10 10 v impedance 1, 2, 3 -- 23 -- k ? capacitance 2 2. guarenteed by design -- -- 35 -- pf t able 6. 7805alp t hroughput s peed (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit conversion time 9, 10, 11 -- 7.6 8 s complete cycle (acquire and convert) 9, 10, 11 -- -- 10 s throughput rate 1 1. guaranteed by design 100 -- -- khz t able 7. 7805alp ac a ccuracy s pecifications (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter t est c onditions s ubgroups m in t yp m ax u nit spurious-free dynamic range 1,2 1. all specifications in db are referred to a full-scale 10v input. 2. guaranteed by design. f in = 45 khz 4, 5, 6 90 -- -- db total harmonic distortion 1,2 f in = 45 khz 4, 5, 6 -- -- -90 db signal-to-(noise + distortion) 1,2 f in = 45 khz 4, 5, 6 83 -- -- db -60db input 4, 5, 6 -- 30 -- signal-to-noise 1,2 f in = 45 khz 4, 5, 6 83 -- -- db full-power bandwidth 3 3. full-power bandwidth defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 db or 10 bi ts of accuracy. 4, 5, 6 -- 250 -- khz t able 4. 7805alp d igital i nputs (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit
m e m o r y 5 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 t able 8. 7805alp s ampling d ynamics (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter t est c onditions s ubgroups m in t yp m ax u nit aperture delay 9, 10, 11 -- 40 -- ns transient response fs step 9, 10, 11 -- 2 -- s overvoltage recovery 1 1. recovers to specified performance after 2 x f s input overvoltage. 9, 10, 11 -- 150 -- ns t able 9. 7805alp r eference t able 10. (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit internal reference voltage 1, 2, 3 2.48 2.5 2.52 v internal reference source current (must use external buffer) 1, 2, 3 -- 1 -- a internal reference drift 1, 2, 3 -- 8 -- ppm/ c external reference voltage range for specified linearity 1 1. tested by application of signal. 1, 2, 3 -- 2.5 -- v external reference current drain 2 2. guaranteed by design -- -- -- 100 a t able 11. 7805alp d igital o utputs (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter t est c onditions s ubgroups m in t yp m ax u nit data formatting (parallel 16-bits binary two?s complement) data coding binary two?s complement v ol (i sink = 1.6ma) 4.0 1, 2, 3 -- -- 0.4 v v oh (i source = -400 a) 1, 2, 3 4.0 -- -- v leakage current high-z state, v out = 0v to v s 1, 2, 3 -- -- 5 a output capacitance 1 1. guarenteed by design high-z state -- -- 10 -- pf
m e m o r y 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 t able 12. 7805alp p ower s upplies (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter t est c onditions s ubgroups m in t yp m ax u nit v s -- 4.8 5 5.25 v i s 1, 2, 3 -- 20.3 -- ma power dissipation f s = 100 khz 1, 2, 3 -- 102 132.0 mw t able 13. 7805alp d igital t iming (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) p arameter s ubgroups m in t yp m ax u nit bus access time 9, 10, 11 -- -- 83 ns bus relinquish time 9, 10, 11 -- -- 83 ns t able 14. 7805alp t emperature p arameter m in t yp m ax u nit specified performance -40 -- 85 c derated performance 1 1. tested by application of signal. -55 -- 125 c storage -65 -- 150 c t able 15. 7805alp c onversion t iming 1 (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) d escription s ymbol s ubgroups m in t yp m ax u nit convert pulse width t 1 9, 10, 11 40 -- 7000 ns data valid delay after r/c low t 2 9, 10, 11 -- -- 8 s busy delay from r/c low t 3 9, 10, 11 -- -- 85 ns busy low t 4 9, 10, 11 -- -- 8 s busy delay after end-of-conversion t 5 9, 10, 11 -- 220 -- ns aperture time t 6 9, 10, 11 -- 40 -- ns conversion time t 7 9, 10, 11 -- 7.6 8 s acquisition time t 8 9, 10, 11 -- -- 2 s throughput time t 7 + t 8 9, 10, 11 -- 9 10 s bus relinquish time t 9 9, 10, 11 10 35 83 ns
m e m o r y 7 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 busy delay after data valid t 10 9, 10, 11 50 200 -- ns previous data valid delay after r/c low t 11 9, 10, 11 -- 7.4 -- s r/c to cs setup time t 12 9, 10, 11 10 -- -- ns time between conversions t 13 9, 10, 11 10 -- -- s bus access time t 14 9, 10, 11 10 -- 83 ns 1. tested by application of signal. t able 16. 7805alp c ontrol l ine f unction for r ead and c onvert cs r/c busy o peration 1 x x none. databus is in hi-z state. " 0 1 initiates conversion "n". databus remains in hi-z state. 0 " 1 initiates conversion "n". databus enters hi-z state. 01 conversion "n" completed. valid data from conversion "n" on the databus. " 1 1 enables databus with valid data from conversion "n". " 1 0 enables databus with valid data from conversion "n-1". conversion "n" in progress. 0 0 enables databus with valid data from conversion "n-1". conversion "n" in progress." 00 new conversion initiated without acquisition of a new signal. data will be invalid. cs and/or r/c must be high when busy goes high. x x 0 new convert commands ignored. conversion "n" in progress. t able 15. 7805alp c onversion t iming 1 (v s = 5v, t a = -40 to +85 c u nless o therwise s pecified ) d escription s ymbol s ubgroups m in t yp m ax u nit
m e m o r y 8 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 f igure 1. c onversion t iming with o utputs e nabled after c onversion (cs tied low) f igure 2. u sing cs to c ontrol c onversion and r ead t iming lpt ? operation latchup protection technology (lpt ? ) automatically detects an increase in the supply current of the 7805alp con- verter due to a single event effect and internally cycles the power to the converter off, then on, which restores the
m e m o r y 9 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 steady state operation of the device. a simplified block diagram of the 7805alp circuitry is shown in figure 1. the cir- cuitry consists of a protected device, the ads7805 die, a current sensor, a power switch, and a status output driver. f igure 3. l atchup p rotection d iagram differences between the7805a and the ads7805 because the 7805a uses the ads7805 die to perform the analog to digital conversion function its operation and per- formance is very similar to the ads7805 packaged part from burr-brown. in general the operation and application will be the same for both parts. there are two primary differences: the operation of the supply pins and the operation of the byte and status pins. the ads7805 provides separate analog and digital supply pins. the 7805a provides a single supply input v s pin in place of the v dig pin which powers both the analog and digital circuitry through the lpt ? current sensor and power switch. the v s power supply should be treated as an analog supply and isolated from noise on the system digital power supply. the low side of the power switch connects to the ads7805 die power pads and to the package dec- plng pin which replaces the vana pin. the decplng pin allows low esr ceramic capacitors to directly decouple the ads7805 die. caution: the decplng pin must not be connected to the power supply since this will defeat the lpt ? power switch and could result in latchup of the device during operation in a radiation environment. electrolytic capacitors should not be connected to the decplng pin because the large capacitance will increase the recovery time of the 7805a. the primary functional difference between the ads7805 and the 7805a is that the byte signal of the ads7805 is internally grounded and the pin function is replaced by the status output. grounding the byte signal permanently assigns the data output signal bits 15:0 as shown in the 7805a pinout diagram where bit15 is the msb and bit 0 is the lsb. a high level status signal indicates that a single event induced latchup current was detected by the lpt ? circuitry causing power to be removed from the protected device. caution: during the time that power is removed from the protected device, it is critical that external circuitry driving the device i/o pins does not backdrive the device supply. backdriving the supply could contribute to an extended or even a permanent latchup condition. vs i/os power switch protected device status output decplng vdig vana byte ads7805 7805alprp dgnd agnd2 agnd1 current sensor status driver
m e m o r y 10 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 in order to prevent backdriving the supply, the status signal should be used in the system to tri-state or gate external i/o drive circuits to a low state. similarly, if the data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data bus) must not be less than 10 k ? typical to assure proper single event effect recovery. tri-stating of inputs should occur within 100 nsec after the rise of the status pin. the byte signal can be made available in place of the status signal at customer request. status can also be used to generate an input to the system data processor indicating that an lpt ? cycle has occurred, and the protected device output accuracy may not be met until after the respective recovery time to the event. the status signal is generated from an advanced cmos logic gate output. this output may not exhibit a monotonic falltime and may even oscillate briefly while power is being restored to the protected device and the decou- pling capacitance is charged. loading on the status output should be minimized because this signal is used inter- nally by the 7805a. it is recommended that load current not exceed 2 ma and load capacitance be kept well below 1000 pf. a summary of the pin differences between the ads7805 and 7805a is provided below. example circuits for using the 7805a figure 2 shows a typical application circuit for using the 7805a as an input to a digital data processor. this circuit shows the use of the status pin to tri-state the control inputs when the latchup protection circuit cycles the power to the protected ads7805 die. figure 3 shows a typical application circuit for connecting the 7805a to a 16-bit data bus with multiple drivers on the bus. tri-state buffers are used to isolate the 7805a data outputs from the data bus. figure 4 shows the typical applica- tion circuit for connecting the 7805a to an 8-bit data bus. t able 16. p in d ifferences p in n umber ads7805 7805a p in d ifference d escription 23 byte status a high level status signal indicates that power is removed from the ads7805 die. i/o pins must not be driven high while this signal is active. the byte signal of the ads7805 die is internally grounded but can also be made available in place of the status pin at customer request. 27 vana decplng the ads7805 vana and v dig die pads are connected together and are available at the decplng pin. this pin allows external ceramic capacitors to directly decou- ple the power inputs to the ads7805 die-to-analog ground. decoupling capaci- tance should not exceed 0.2 uf typical. this pin must not be connected to a power supply directly since this will defeat the latchup protection circuitry. electrolytic filter capacitors should not be connected to this pin but should be connected between the v s pin and ground. 28 v dig v s this is the power supply input for the lpt circuitry and the protected ads7805 die. this supply should be treated as an analog supply with filtering and/or isolation from the noisy system digital power supply. the lpt latchup current sense and power switch circuitry is located between this pin and the decplng pin.
m e m o r y 11 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 f igure 4. t ypical 7805a a pplication c ircuit f igure 5. t ypical 7805a c ircuit with 16- bit b us i nterface
m e m o r y 12 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 f igure 6. t ypical 7805a c ircuit with 8- bit b us i nterface testing the 7805a latchup protection circuitry the decplng pin provides direct access to the 7805alp converter supply pins for attaching external decoupling capacitor(s) to ground. this pin can also be used to test the lpt ? operation by sinking a pulsed current load to ground as shown in the test circuit in figure 5 and as described in the lpt operating characteristics table (table 17) and lpt timing diagram (figure 7). this test approximates the operation of the 7805a in response to a single event latchup and recovery. during the time that the power is cycled, output signals and data from the 7805a are invalid. the status signal high indicates that power is removed from the ads7805 die. all input pins must be driven low or tri-stated. when this signal is low, power is applied to the ads7805 die. the status signal can be used to measure the supply recovery time. the status signal can exhibit multiple transitions when power is re-applied and the decoupling capacitors are charged. the duration and number of transitions is dependent on the amount of capacitance used. the supply recovery time interval starts when the supply current rises (causing status to go high) and ends when the status signal stabi- lizes low again. within the functional recovery time interval (typically 25 sec after the lpt circuit reapplies power), the normal func- tional operation of the converter is restored with less than 5% full scale error. additional settling time is then required to return to full accurate operation. defined recovery time intervals indicate that time to recover first is within 8-bit accu- racy, then within 12 bit accuracy, and finally full 16-bit accuracy. these recovery times are primarily due to the single event and power cycling effects on the reference circuits and the settling times of their respective filter capacitors. t able 17. lpt ? o perating c haracteristics p arameter m in t yp m ax u nits supply threshold current - ithr 56 77 99 ma protection time (is peak = .2a) - tpt -- 1 -- sec input tri-state time - tioff -- -- 100 nsec
m e m o r y 13 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 f igure 7. lpt ? t est c ircuit status instability time - tinst -- -- 10 sec supply recovery time (is peak = .2a) - tsr 25 50 100 sec functional recovery time (is peak = .2a) - tfr -- tsr + 25 -- sec 8-bit accuracy recovery time (is peak = .2a) - t8r -- 75 -- msec 12-bit accuracy recovery time (is peak = .2a) - t12r -- 250 -- msec full accuracy recovery time (is peak - .2a) - tfar -- 425 -- msec t able 17. lpt ? o perating c haracteristics p arameter m in t yp m ax u nits
m e m o r y 14 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 f igure 8. f igure 9. seu and sel c ross s ection
m e m o r y 15 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 note: all dimensions in inches 28 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.177 0.192 0.207 b 0.015 0.017 0.022 c 0.004 0.005 0.009 d -- 0.800 0.808 e 0.400 0.410 0.420 e1 -- -- 0.440 e2 0.295 0.300 -- e3 0.000 0.055 -- e 0.050 bsc l 0.390 0.400 0.410 q 0.028 0.032 0.036 s1 0.000 0.067 -- n28
m e m o r y 16 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 note: all dimensions in inches 28-p in r ad -p ak ? d ual i n l ine p ackage s ymbol d imension m in n om m ax a -- 0.185 0.225 b 0.014 0.018 0.026 b2 0.045 0.050 0.065 c 0.008 0.010 0.018 d -- 1.600 1.616 e 0.585 0.595 0.605 ea 0.600 bsc ea/2 0.300 bsc e 0.100 bsc l 0.165 0.175 0.185 q 0.015 0.030 0.075 s1 0.005 0.125 -- s2 0.005 -- -- n28
m e m o r y 17 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 16-bit latchup protected adc 7805alp 01.10.05 rev 9 important notice: these data sheets are created using the chip manufacturer?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

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